Wei Zhejia leads the opening of the first stop of TSMC Technology Forum in North America, announcing the A16 advanced process and multiple technologies | TechNews Technology News

TSMC’s 2024 North American Technology Forum, which opened on the 24th, revealed the latest manufacturing processes, advanced packaging, and three-dimensional integrated circuit (3D IC) technology, leveraging leading semiconductor technology to drive the next generation of artificial intelligence (AI) innovation.

TSMC A16 was announced for the first time at the TSMC North American Technology Forum, which combines leading nanosheet transistors and innovative backside power rail solutions to significantly increase logic density and performance. It will be mass-produced in 2026. The other system-level wafer (TSMC-SoWTM) brings revolutionary wafer-level performance advantages to meet the AI ​​needs of ultra-large-scale data centers.

Coinciding with the 30th anniversary of the TSMC North America Technology Forum, the number of attendees increased from less than 100 30 years ago to more than 2,000 this year. The North American Technology Forum was held in Santa Clara, California, kicking off the global technology forum in the coming months and also setting up an innovation area to showcase the achievements of emerging customers.

President Wei Zhejia pointed out that in an AI-empowered world, artificial intelligence is not only in data centers, but also built into personal computers, mobile devices, automobiles, and the Internet of Things. TSMC provides the most complete technologies, from the world’s most advanced silicon wafers to the most extensive advanced packaging portfolio and 3D IC platforms, to special process technologies that connect the digital world and the real world to realize the AI ​​vision.

New technologies include:

TSMC A16

N3E enters mass production and N2 enters mass production in the second half of 2025. TSMC launches new technology A16. A16 combines the Super PowerRail architecture and nanosheet transistors and will be mass-produced in 2026. The super power rail moves the power supply network to the back of the wafer, freeing up more signal network space on the front of the wafer, improving logic density and performance, making A16 suitable for high-performance computing (HPC) products with complex signal routing and dense power supply networks. . Compared with TSMC’s N2P process, A16’s speed is increased by 8% to 10% at the same Vdd (operating voltage), power consumption is reduced by 15% to 20% at the same speed, and chip density is increased by up to 1.10 times, supporting data center products.

TSMC’s innovative NanoFlex supports nanosheet transistors

TSMC N2 will be paired with TSMC NanoFlex, demonstrating a new breakthrough in synergistic optimization of TSMC’s design technology. TSMC NanoFlex provides chip designers with flexible N2 standard components, which are the basic building blocks of chip design. Lower-height components can save area and have higher power consumption efficiency, while higher-height components maximize performance. The same design block optimizes the combination of high and low components to adjust application power consumption, performance and area to achieve the best balance.

N4C

In response to wider applications, TSMC N4C continues N4P, reducing die costs by up to 8.5% and having a low threshold, and will be mass-produced in 2025. N4C has area-effective basic silicon intellectual property and design rules, and is fully compatible with N4P. Customers can easily switch to N4C. The reduction in die size also improves yield, providing a cost-effective choice for products that emphasize value. Upgrade to TSMC’s next advanced technology.

CoWoS, system integrated chip, system level wafer (TSMC-SoW)

TSMC CoWoS is a key technology for the AI ​​revolution, placing more processor cores and high-bandwidth memory (HBM) side by side on a single interposer. TSMC System Integrated Chip (SoIC) has become the leading solution for 3D chip stacking, and customers tend to use CoWoS with SoIC and other components to achieve system-in-package (SiP) integration.

TSMC’s system-level wafers provide innovative options that allow 12-inch wafers to accommodate a large number of dies, provide more computing power, significantly reduce data center space, and increase performance per watt by several levels. TSMC’s first SoW product uses logic chips as the main integrated fan-out (InFO). The CoWoS chip stacked version will be ready in 2027, integrating SoIC, HBM and other components to create a powerful and computing power comparable to a data center server rack. Even wafer-level systems for entire servers.

Silicon Photonics Integration

TSMC is developing the Compact Universal Photon Engine (COUPETM) to support the explosive growth of data transmission caused by the AI ​​boom. COUPE uses SoIC-X chip stacking to stack electronic dies on photonic dies. Compared with traditional stacking, the die-to-die interface has the lowest resistance and higher energy efficiency. The COUPE verification supporting small plug-in connectors will be completed in 2025. In 2026, CoWoS packaging will be integrated into Co-Packaged Optics (CPO), and optical connections will be directly introduced into the packaging.

Advanced packaging for automotive use

After launching the N3AE process to support automotive customers in 2023, TSMC will continue to meet the needs of automotive customers by integrating advanced chips and packaging to meet driving safety and quality requirements. TSMC is developing InFO-oS and CoWoS-R solutions to support advanced driver assistance systems (ADAS), vehicle control and central control computers, etc., and will complete AEC-Q100 Level 2 verification in the fourth quarter of 2025.

(Source of first picture: TSMC)