(Central News Agency reporter Zhang Jianzhong, Hsinchu, 25th) TSMC North America Technology Forum debuted, revealing the latest process technology, advanced packaging technology and three-dimensional integrated circuit (3D IC) technology. Semiconductor industry experts pointed out that A16 technology, super rails and system-level wafers are the three highlights of TSMC’s technology forum, fully demonstrating its continued technological leadership.
Yang Ruilin, research director of the International Institute of Obstetrics and Mechanics of ITRI, said that unlike Samsung, which switched to a gate-around gate (GAA) architecture in its 3-nanometer process, TSMC’s (2330) 3-nanometer process technology still uses fin field effect transistors ( FinFET) architecture, 2nm process technology changed to nanosheet architecture.
Yang Ruilin said that changing the transistor architecture from FinFET to nanosheets is a major change. With TSMC’s 2-nanometer process technology set to be mass-produced in the second half of 2025, he believes that TSMC is making smooth progress in converting the nanosheet architecture.
Yang Ruilin said that TSMC’s newly announced A16 technology will combine nanosheet transistors and Super Power Rail architecture and is expected to be mass-produced in 2026. Among them, super rail technology moves the power supply network to the back of the wafer, freeing up more layout space for signal networks on the front of the wafer, thereby improving logic density and performance.
Intel named this crystal back power supply technology PowerVia and announced its development first. Yang Ruilin said that this time TSMC detailed the performance of the A16 technology using super rails in terms of chip density, which shows that the technology is developing smoothly and has a high degree of readiness.
TSMC pointed out that compared with the 2nm N2P process, A16 technology is 8% to 10% faster at the same operating voltage; at the same speed, power consumption is reduced by 15% to 20%, and the chip density is increased by 1.1 times. Suitable for high-performance computing (HPC) products with complex signal routing and dense power supply networks.
Yang Ruilin said that TSMC’s system-on-wafer (SoW) technology is the key technology to achieve a graphics processor (GPU) with 1 trillion transistors, which can stack multiple logic ICs.
TSMC pointed out that SoW technology allows 12-inch wafers to accommodate a large number of dies, provide more computing power, significantly reduce data center space usage, and improve performance per watt. The chip-stacked version using CoWoS technology is expected to be ready in 2027, which can integrate system integrated chips (SoIC), high-bandwidth memory (HBM) and other components to create a powerful and computing power comparable to a data center server rack or an entire server. wafer-level systems.
Yang Ruilin said that TSMC has fully demonstrated its technological leadership, which will exert a magnetic attraction effect and improve customer stability. TSMC also launches “high-quality and low-cost” process technology for customers with different needs, which will help further consolidate customer relationships. (Editor: Lin Shuyuan) 1130425
